Conventionally, a semiconductor package using a leadframe as a chip carrier, which is referred to as a leadframe-based semiconductor package, is formed by attaching a non-active surface of a semiconductor chip to a die pad of the leadframe, electrically connecting the semiconductor chip to a plurality of leads of the leadframe via a plurality of bonding wires, and forming an encapsulant to encapsulate the semiconductor chip, the bonding wires and a part of the leadframe. However, this type of semiconductor package usually encounters problems that, for example, electronic signals become weakened due to the length of the bonding wires, and during a molding process of forming the encapsulant, wire loops of the bonding wires tend to be swept or sagged due to impact of mold flow of an encapsulating resin, thereby leading to undesirable contact and short circuit between adjacent bonding wires. Moreover, the leadframe-based semiconductor package cannot be further reduced in thickness as the height of the wire loops of the bonding wires must be considered.
Accordingly, there has been proposed another leadframe-based semiconductor package using a flip-chip technology. In this semiconductor package, a semiconductor chip is mounted on a leadframe in an upside-down manner that a plurality of conductive bumps implanted to an active surface of the semiconductor chip are bonded and electrically connected to corresponding leads of the leadframe. Consequently, without the use of bonding wires, a path for transmitting electronic signals in the semiconductor package is shortened through the conductive bumps and the quality of electronic signals during transmission is not adversely affected, and further, the semiconductor package can be effectively reduced in height as not having to consider the loop height of the bonding wires.
However, in the above leadframe-based flip-chip type semiconductor package, the leads of the leadframe are disposed at a peripheral portion of the leadframe, and there is no electrical connection provided at a central portion of the leadframe, such that an issue of not having a sufficient number of electrical connections may arise.
In order to solve the aforementioned problem, U.S. Pat. No. 6,815,833 proposes a semiconductor package 1 having electrical connections formed at a central portion of a leadframe. As shown in FIGS. 1A and 1B, the semiconductor package 1 comprises: a leadframe 17 having a plurality of leads 14 and a die pad 15; a semiconductor chip 11 having an active surface 112, the semiconductor chip 11 being mounted and electrically connected to the die pad 15 and the leads 14 of the leadframe 17 by a plurality of conductive bumps 12 formed on the active surface 112 of the semiconductor chip 11; and an encapsulant 16 for encapsulating a part of the leadframe 17, the conductive bumps 12 and the semiconductor chip 11, wherein bottom surfaces of the leads 14 and the die pad 15 are exposed from the encapsulant 16. By this arrangement, the leads 14 of the leadframe 17 serve as input/output (I/O) connections, and the die pad 15 of the leadframe 17 serves as, for example, an additional power or grounding connection.
U.S. Pat. No. 6,597,059 also proposes a semiconductor package 2 with an increased number of electrical connections. As shown in FIGS. 2A and 2B, the semiconductor package 2 comprises: a leadframe 27 having a plurality of leads 24 and two die pads 25; a semiconductor chip 21 having an active surface 212, the semiconductor chip 21 being electrically connected to the corresponding leads 24 and the two die pads 25 by a plurality of conductive bumps 22 formed on the active surface 212 of the semiconductor chip 21; and an encapsulant 26 for encapsulating a part of the leadframe 27, the conductive bumps 22 and the semiconductor chip 21, wherein bottom surfaces of the leads 24 and the die pads 25 are exposed from the encapsulant 26. By such arrangement, the leads 24 of the leadframe 27 serve as I/O connections, and the two die pads 25 of the leadframe 27 serve as, for example, two additional power and/or grounding connections.
Although in the above-mentioned packages, it seems beneficial of having the die pad(s) provide one or two additional electrical connections besides the leads of the lead frame, the die pad(s) may only serve as power or grounding connection(s) but not I/O connection(s) because a plurality of conductive bumps are electrically connected thereto, such that this arrangement still does not fulfill the need of sufficient I/O connections for a highly integrated semiconductor chip with high electrical performance and multi-functionality. Therefore, the problem to be solved here is to provide a semiconductor package with an increased number of I/O connections so as to enhance the electrical performance of the semiconductor package.